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1 date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation sp3223eb/3243eb intelligent +3.0v to +5.5v rs-232 transceivers the sp3223eb and sp3243eb products are rs-232 transceiver solutions intended for portable or hand-held applications such as notebook and palmtop computers. the sp3223eb and sp3243eb use an internal high-efficiency, charge-pump power supply that requires only 0.1 f capacitors in 3.3v operation. this charge pump and sipex's driver architecture allow the sp3223eb/3243eb series to deliver compliant rs-232 performance from a single power supply ranging from +3.0v to +5.5v. the sp3223eb is a 2-driver/2-receiver device, and the sp3243eb is a 3-driver/5-receiver device ideal for laptop/notebook computer and pda applications. the sp3243eb includes one complementary receiver that remains alert to monitor an external device's ring indicate signal while the device is shutdown. the auto on-line?feature allows the device to automatically "wake-up" during a shutdown state when an rs-232 cable is connected and a connected peripheral is turned on. otherwise, the device automatically shuts itself down drawing less than 1 a. meets true eia/tia-232-f standards from a +3.0v to +5.5v power supply interoperable with eia/tia-232 and adheres to eia/tia-562 down to a +2.7v power source auto on-line circuitry automatically wakes up from a 1 a shutdown minimum 250kbps data rate under load regulated charge pump yields stable rs-232 outputs regardless of v cc variations enhanced esd specifications: +15kv human body model + 15kv iec1000-4-2 air discharge + 8kv iec1000-4-2 contact discharge description selection table applicable u.s. patents - 5,306,954; and other patents pending. e c i v e ds e i l p p u s r e w o p2 3 2 - s r s r e v i r d 2 3 2 - s r s r e v i e c e r l a n r e t x e s t n e n o p m o c e n i l - n o o t u a y r t i u c r i c e t a t s - 3 l t tf o . o n s n i p b e 3 2 2 3 p sv 5 . 5 + o t v 0 . 3 +22s r o t i c a p a c 4s e ys e y0 2 b e 3 4 2 3 p sv 5 . 5 + o t v 0 . 3 +35s r o t i c a p a c 4s e ys e y8 2 v- 1 2 3 4 17 18 19 20 5 6 7 16 15 14 shutdown c1+ v+ c1- c2+ c2- online en r 1 in gnd v cc t 1 out status 8 9 10 11 12 13 r 2 in r 2 out sp3223eb t 2 out t 1 in t 2 in r 1 out now available in lead free packaging
date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation 2 parameter min. typ. max. units conditions dc characteristics supply current, 1.0 10 a all rxin open, online = gnd, auto on-line shutdown = v cc , txin = v cc or gnd,v cc = +3.3v, t amb = +25 c supply current, shutdown 1.0 10 a shutdown = gnd, v cc = +3.3v, t amb = +25 c, txin = v cc or gnd supply current, 0.3 1.0 ma online = shutdown = v cc , auto on-line disabled txin = v cc or gnd, no load, v cc = +3.3v, t amb = +25 c logic inputs and receiver outputs input logic threshold v cc = +3.3v or +5.0v, txin, low gnd 0.8 v en (sp3223eb), online, high 2.4 vcc v shutdown input leakage current 0.01 1.0 a txin, en (sp3223eb), online, shutdown, t amb = +25 c, v in = 0v to v cc output leakage current 0.05 10 a receivers disabled, v out = 0v to v cc output voltage low 0.4 v i out = 1.6ma output voltage high v cc - 0.6 v cc - 0.1 v i out = -1.0ma driver outputs output voltage swing 5.0 5.4 v all driver outputs loaded with 3k ? to gnd, t amb = +25 c output resistance 300 ? v cc = v+ = v- = 0v, v out = 2v output short-circuit current 35 60 ma v out = 0v output leakage current 25 av cc = 0v or 3.0v to 5.5v, v out = 12v, drivers disabled note 1 : v+ and v- can have maximum magnitudes of 7v, but their absolute difference cannot exceed 13v. absolute maximum ratings these are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. v cc ...................................................... -0.3v to +6.0v v+ (note 1) ...................................... -0.3v to +7.0v v- (note 1) ....................................... +0.3v to -7.0v v+ + |v-| (note 1) ........................................... +13v i cc (dc v cc or gnd current) ......................... +100ma input voltages txin, online, shutdown, en ( sp3223e ) ............ -0.3v to +6.0v rxin .................................................................. +25v output voltages txout ........................................................... +13.2v rxout, status ..................... -0.3v to (v cc + 0.3v) unless otherwise noted, the following specifications apply for v cc = +3.0v to +5.5v with t amb = t min to t max , c1 - 4 = 0.1 f. typical values apply at v cc = +3.3v or +5.0v and t amb = 25 c. electrical characteristics short-circuit duration txout .................................................... continuous storage temperature ...................... -65 c to +150 c power dissipation per package 28-pin pdip (derate 16.0mw/ c above+70 c) ...................... 1300mw 20-pin ssop (derate 9.25mw/ c above +70 c) ...................... 750mw 20-pin tssop (derate 11.1mw/ c above +70 c) ....................... 900mw 28-pin soic (derate 12.7mw/ c above +70 c) .................... 1000mw 28-pin ssop (derate 11.2mw/ c above +70 c) ...................... 900mw 28-pin tssop (derate 11.1mw/ c above +70 c) ....................... 900mw 32-pin qfn
3 date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation electrical characteristics unless otherwise noted, the following specifications apply for v cc = +3.0v to +5.5v with t amb = t min to t max , c1 - 4 = 0.1 f. typical values apply at v cc = +3.3v or +5.0v and t amb = 25 c. parameter min. typ. max. units conditions receiver inputs input voltage range -25 25 v input threshold low 0.6 1.2 v v cc = 3.3v input threshold low 0.8 1.5 v v cc = 5.0v input threshold high 1.5 2.4 v v cc = 3.3v input threshold high 1.8 2.4 v v cc = 5.0v input hysteresis 0.3 v input resistance 3 5 7 k ? auto on-line circuitry characteristics (online = gnd, shutdown = v cc ) status output voltage low 0.4 v i out = 1.6ma status output voltage high v cc - 0.6 v i out = -1.0ma receiver threshold to drivers enabled (t online ) 200 s figure 20 receiver positive or negative 0.5 s figure 20 threshold to status high (t stsh ) receiver positive or negative 20 s figure 20 threshold to status low (t stsl ) timing characteristics maximum data rate 250 kbps r l = 3k ? , c l = 1000pf, one driver active receiver propagation delay t phl 0.15 s receiver input to receiver output, t plh 0.15 c l = 150pf receiver output enable time 200 ns normal operation receiver output disable time 200 ns normal operation driver skew 100 ns | t phl - t plh |, t amb = 25 c receiver skew 50 ns | t phl - t plh | transition-region slew rate 30 v/ sv cc = 3.3v, r l = 3k ? , t amb = 25 c, measurements taken from -3.0v to +3.0v or +3.0v to -3.0v
date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation 4 figure 1. transmitter output voltage vs. load capacitance for the sp3223eb figure 2. slew rate vs. load capacitance for the sp3223eb typical performance characteristics unless otherwise noted, the following performance characteristics apply for v cc = +3.3v, 250kbps data rate, all drivers loaded with 3k ? , 0.1 f charge pump capacitors, and t amb = +25 c. 30 25 20 15 10 5 0 0 500 1000 2000 3000 4000 5000 slew rate (v/ s) load capacitance (pf) - slew + slew 1 transmitter at 250kbps 1 transmitter at 15.6kbps all drivers loaded 3k + load cap 35 30 25 20 15 10 5 0 i cc (ma) load capacitance (pf) 0 1000 2000 3000 4000 5000 250kbps 125kbps 20kbps 1 transmitter at 250kbps 1 transmitter at 15.6kbps all drivers loaded 3k + load cap figure 3. supply current vs. load capacitance when transmitting data for the sp3223eb figure 4. supply current vs. supply voltage for the sp3243eb 20 15 10 5 0 2.7 3 3.5 4 4.5 5 supply voltage (v dc ) supply current (ma) 1 transmitter at 250kbps 2 transmitters at 15.6kbps all drivers loaded with 3k // 1000pf figure 5. transmitter output voltage vs. supply voltage for the sp3243eb figure 6. transmitter output voltage vs. load capacitance for the sp3243eb 6 4 2 0 -2 -4 -6 0 1000 2000 3000 4000 5000 txout + txout - t ransmitter output v oltage (v dc ) load capacitance (pf) 6 4 2 0 -2 -4 -6 0 1000 2000 3000 4000 5000 txout + txout - t ransmitter output v oltage (v) load capacitance (pf) 6 4 2 0 -2 -4 -6 2.7 3 3.5 4 4.5 5 supply voltage (v dc ) t ransmitter output v oltage (v dc ) txout - txout +
5 date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation typical performance characteristics unless otherwise noted, the following performance characteristics apply for v cc = +3.3v, 250kbps data rate, all drivers loaded with 3k ? , 0.1 f charge pump capacitors, and t amb = +25 c. figure 7. slew rate vs. load capacitance for the sp3243eb 25 20 15 10 5 0 0 500 1000 2000 3000 4000 5000 slew rate (v/ s) load capacitance (pf) - slew + slew 1 transmitter at 250kbps 2 transmitter at 15.6kbps all drivers loaded 3k + load cap figure 8. supply current vs. load capacitance when transmitting data for the sp3243eb 40 35 30 25 20 15 10 5 0 supply current (ma) load capacitance (pf) 0 1000 2000 3000 4000 5000 250kbps 120kbps 20kbps 1 transmitter at full data rate 2 transmitters at 15.5 kbps all transmitters loades 3k + load cap 6 4 2 0 -2 -4 -6 2.7 3 3.5 4 4.5 5 supply voltage (v dc ) t ransmitter output v oltage (v) txout - txout + figure 9. supply current vs. supply voltage for the sp3243eb figure 10. transmitter output voltage vs. supply voltage for the sp3243eb 25 20 15 10 5 0 2.7 3 3.5 4 4.5 5 supply voltage (v dc ) supply current (ma) 1 transmitter at 250kbps 2 transmitters at 15.6kbps all drivers loaded with 3k // 1000pf
date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation 6 table 1. device pin description pin number sp3243eb soic, ssop, sp3243ebcr name function sp3223eb tssop qfn en receiver enable. apply logic low for normal operation. 1 - - apply logic high to disable the receiver outputs (high-z state). c1+ positive terminal of the voltage doubler charge-pump capacitor. 2 28 28 v+ regulated +5.5v output generated by the charge pump. 3 27 26 c1- negative terminal of the voltage doubler charge-pump capacitor. 4 24 22 c2+ positive terminal of the inverting charge-pump capacitor. 5 1 29 c2- negative terminal of the inverting charge-pump capacitor. 6 2 31 v- regulated -5.5v output generated by the charge pump. 7 3 32 r 1 in rs-232 receiver input. 16 4 2 r 2 in rs-232 receiver input. 9 5 3 r 3 in rs-232 receiver input. - 6 4 r 4 in rs-232 receiver input. - 7 5 r 5 in rs-232 receiver input. - 8 6 r 1 out ttl/cmos receiver output. 15 19 17 r 2 out ttl/cmos receiver output. 10 18 16 r 2 out non-inverting receiver-2 output, active in shutdown. - 20 18 r 3 out ttl/cmos receiver output. - 17 15 r 4 out ttl/cmos receiver output. - 16 14 r 5 out ttl/cmos receiver output. - 15 13 status ttl/cmos output indicating online and shutdown status. 11 21 19 t 1 in ttl/cmos driver input. 13 14 12 t 2 in ttl/cmos driver input. 12 13 11 t 3 in ttl/cmos driver input. - 12 10 online apply logic high to override auto-online circuitry keeping 14 23 21 drivers active (shutdown must also be logic high, refer to table 2). t 1 out rs-232 driver output. 17 9 7 t 2 out rs-232 driver output. 8 10 8 t 3 out rs-232 driver output. - 11 9 gnd ground. 18 25 23 v cc +3.0v to +5.5v supply voltage. 19 26 25 shutdown apply logic low to shut down drivers and charge pump. 20 22 20 this overrides all auto on-line circuitry and online (refer to table 2). nc no connection - - 1,24,27,30
7 date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation figure 12. sp3243eb pinout configuration figure 11. sp3223eb pinout configuration v- 1 2 3 4 17 18 19 20 5 6 7 16 15 14 shutdown c1+ v+ c1- c2+ c2- online en r 1 in gnd v cc t 1 out status 8 9 10 11 12 13 r 2 in r 2 out sp3223eb t 2 out t 1 in t 2 in r 1 out r 4 in 1 2 3 4 25 26 27 28 5 6 7 24 23 22 shutdown c2- v- r 1 in r 2 in r 3 in online c2+ c1- gnd v cc v+ status t 1 in 8 9 10 11 18 19 20 21 12 13 14 17 16 15 r 5 out t 1 out t 2 out t 3 out t 3 in t 2 in r 4 out r 5 in r 3 out r 2 out r 1 out r 2 out sp3243eb c1+ figure 13. sp3243eb qfn (qfn) pinout configuration sp3243eb v- c2- nc c2+ c1+ nc v+ v cc nc r 1 in r 2 in r 3 in r 4 in r 5 in t 1 out t 2 out t 3 out t 3 in t 2 in t 1 in r 5 out r 4 out r 3 out r 2 out 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 nc gnd c1- online shutdown status r 2 out r 1 out
date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation 8 figure 14. sp3223eb typical operating circuit sp3223eb 2 4 6 5 3 7 19 gnd t 1 in t 2 in c1+ c1- c2+ c2- v+ v- v cc 13 12 0.1 f 0.1 f 0.1 f + c2 c5 c1 + + c3 c4 + + 0.1 f 0.1 f 17 8 rs-232 outputs rs-232 inputs ttl/cmos inputs +3.3v to +5v 18 shutdown 20 5k ? r 1 out 15 16 5k ? r 2 in r 2 out 10 9 ttl/cmos outputs en 1 online 14 r 1 in t 2 out t 1 out 11 status v cc to p supervisor circuit
9 date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation figure 15. sp3243eb typical operating circuit sp3243eb 28 24 2 1 27 3 26 5k ? 5k ? 5k ? 5k ? 5k ? gnd c1+ c1- c2+ c2- v+ v- v cc 14 13 12 20 19 18 17 16 15 0.1 f 0.1 f 0.1 f + c2 c5 c1 + + c3 c4 + + 0.1 f 0.1 f 9 10 11 4 5 6 7 8 rs-232 outputs rs-232 inputs ttl/cmos inputs ttl/cmos outputs to p supervisor circuit 23 22 21 v cc v cc 25 t 1 in r 1 out r 1 in t 2 out r 2 out t 2 in t 3 in t 3 out t 1 out r 2 in r 3 in r 4 in r 5 in r 2 out r 3 out r 4 out r 5 out online shutdown status
date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation 10 description the sp3223eb and sp3243eb transceivers meet the eia/tia-232 and itu-t v.28/v.24 com- munication protocols and can be implemented in battery-powered, portable, or hand-held ap- plications such as notebook or palmtop comput- ers. the sp3223eb and sp3243eb devices feature sipex's proprietary and patented (u.s.-- 5,306,954) on-board charge pump circuitry that generates 5.5v rs-232 voltage levels from a single +3.0v to +5.5v power supply. the sp3223eb and sp3243eb devices can operate at a data rate of 250kbps fully loaded. the sp3223eb is a 2-driver/2-receiver device, and the sp3243eb is a 3-driver/5-receiver de- vice ideal for portable or hand-held applications. the sp3243eb includes one complementary always-active receiver that can monitor an external device (such as a modem) in shutdown. this aids in protecting the uart or serial controller ic by preventing forward biasing of the protection diodes where v cc may be disconnected. the sp3223eb and sp3243eb series is an ideal choice for power sensitive designs. the sp3223eb and sp3243eb devices feature auto on-line circuitry which reduces the power supply drain to a 1 a supply current. in many portable or hand-held applications, an rs- 232 cable can be disconnected or a connected peripheral can be turned off. under these condi- tions, the internal charge pump and the drivers will be shut down. otherwise, the system auto- matically comes online. this feature allows de- sign engineers to address power saving concerns without major design changes. theory of operation the sp3223eb and sp3243eb series is made up of four basic circuit blocks: 1. drivers, 2. receivers, 3. the sipex proprietary charge pump, and 4. auto on-line circuitry. drivers the drivers are inverting level transmitters that convert ttl or cmos logic levels to 5.0v eia/ tia-232 levels with an inverted sense relative to the input logic levels. typically, the rs-232 output voltage swing is + 5.4v with no load and + 5v minimum fully loaded. the driver outputs are protected against infinite short-circuits to ground without degradation in reliability. these drivers comply with the eia-tia-232f and all previous rs-232 versions. unused driver inputs should be connected to gnd or v cc . the drivers can guarantee a data rate of 250kbps fully loaded with 3k ? in parallel with 1000pf, ensuring compatibility with pc-to-pc commu- nication software. the slew rate of the driver output is internally limited to a maximum of 30v/ s in order to meet the eia standards (eia rs-232d 2.1.7, paragraph 5). the transition of the loaded output from high to low also meets the monotonicity requirements of the standard. figure 16. interface circuitry controlled by micropro- cessor supervisory circuit sp3243eb 28 24 2 1 27 3 26 5k ? 5k ? 5k ? 5k ? 5k ? gnd c1+ c1- c2+ c2- v+ v- v cc 14 13 12 20 19 18 17 16 15 0.1 f 0.1 f 0.1 f + c2 c5 c1 + + c3 c4 + + 0.1 f 0.1 f 9 10 11 4 5 6 7 8 rs-232 outputs rs-232 inputs 23 22 21 v cc 25 t 1 in r 1 out r 1 in t 2 out r 2 out t 2 in t 3 in t 3 out t 1 out r 2 in r 3 in r 4 in r 5 in r 2 out r 3 out r 4 out r 5 out online shutdown status uart or serial c p supervisor ic txd rts dtr rxd cts dsr dcd ri v cc v in reset
11 date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation the sp3223eb and sp3243eb drivers can main- tain high data rates up to 250kbps fully loaded. figure 17 . shows a loopback test circuit used to test the sp3243eb rs-232 drivers. figure 18 shows the test results of the loopback circuit with all three drivers active at 120kbps with typical rs-232 loads in parallel with 1000pf capacitors. figure 19 shows the test results where one driver table 2. shutdown and en truth tables note: in auto on-line mode where online = gnd and shutdown = v cc , the device will shut down if there is no activity present at the receiver inputs. figure 17. loopback test circuit for rs-232 driver data transmission rates was active at 250kbps and all three drivers loaded with an rs-232 receiver in parallel with a 1000pf capacitor. a solid rs-232 data transmission rate of 250kbps provides compatibility with many designs in personal computer peripherals and lan applications. receivers the receivers convert 5.0v eia/tia-232 levels to ttl or cmos logic output levels. all receivers have an inverting output that can be disabled by using the en pin. figure 18. loopback test circuit all drivers at 120kbps figure 19. loopback test circuit one driver at 250kbps sp3223eb sp3243eb gnd t 1 in t x in c1+ c1- c2+ c2- v+ v- v cc 0.1 f 0.1 f 0.1 f + c2 c5 c1 + + c3 c4 + + 0.1 f 0.1 f ttl/cmos inputs +3v to +5v 18 shutdown 5k ? r 1 out 5k ? r x in r x out ttl/cmos outputs en online r 1 in t x out t 1 out status v cc to p supervisor circuit 1000pf 1000pf device: sp3223eb shutdown en t x out r x out 00 high z active 01 high z high z 10 active active 11 active high z device: sp3243eb shutdown t x out r x out r 2 out 0 high z high z active 1 active active active
date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation 12 receivers are active when the auto on-line circuitry is enabled or when in shutdown. during the shutdown, the receivers will continue to be active. if there is no activity present at the receivers for a period longer than 100 s or when shutdown is enabled, the device goes into a standby mode where the circuit draws 1 a. driving en to a logic high forces the outputs of the receivers into high-impedance. the truth tab le logic of the sp3223eb and sp3243eb driver and receiver outputs can be found in table 2. the sp3243e b includes an additional non-in- verting receiver with an output r 2 out. r 2 out is an extra output that remains active and moni- tors activity while the other receiver outputs are forced into high impedance. this allows ring indicator (ri) from a peripheral to be monitored without forward biasing the ttl/cmos inputs of the other devices connected to the receiver outputs. since receiver input is usually from a transmis- sion line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 300mv. this ensures that the receiver is virtually immune to noisy transmission lines. should an input be left unconnected, an internal 5k ? pulldown resistor to ground will commit the output of the receiver to a high state. charge pump the charge pump is a sipex ?atented design (u.s. 5,306,954) and uses a unique approach compared to older less?fficient designs. the charge pump still requires four external capacitors, but uses a four?hase voltage shifting technique to attain symmetrical 5.5v power supplies. the internal power supply consists of a regulated dual charge pump that provides output voltages 5.5v regardless of the input voltage (v cc ) over the +3.0v to +5.5v range. this is important to maintain compliant rs-232 levels regardless of power supply fluctuations. the charge pump operates in a discontinuous mode using an internal oscillator. if the output voltages are less than a magnitude of 5.5v, the charge pump is enabled. if the output voltages exceed a magnitude of 5.5v, the charge pump is disabled. this oscillator controls the four phases of the voltage shifting. a description of each phase follows. phase 1 ?v ss charge storage ?during this phase of the clock cycle, the positive side of capacitors c 1 and c 2 are initially charged to v cc . c l + is then switched to gnd and the charge in c 1 is transferred to c 2 . since c 2 + is connected to v cc , the voltage potential across capacitor c 2 is now 2 times v cc . phase 2 ?v ss transfer ?phase two of the clock connects the negative terminal of c 2 to the v ss storage capacitor and the positive terminal of c 2 to gnd. this transfers a negative generated voltage to c 3 . this generated voltage is regulated to a minimum voltage of -5.5v. simultaneous with the transfer of the voltage to c 3 , the positive side of capacitor c 1 is switched to v cc and the negative side is connected to gnd. phase 3 ?v dd charge storage ?the third phase of the clock is identical to the first phase ?the charge transferred in c 1 produces ? cc in the negative terminal of c 1 , which is applied to the negative side of capacitor c 2 . since c 2 + is at v cc , the voltage potential across c 2 is 2 times v cc . phase 4 ?v dd transfer ?the fourth phase of the clock connects the negative terminal of c 2 to gnd, and transfers this positive generated voltage across c 2 to c 4 , the v dd storage capacitor. this voltage is regulated to +5.5v. at this voltage, the internal oscillator is disabled. simultaneous with the transfer of the voltage to c 4 , the positive side of capacitor c 1 is switched to v cc and the negative side is connected to gnd, allowing the charge pump cycle to begin again. the charge pump cycle will continue as long as the operational conditions for the internal oscillator are present.
13 date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation since both v + and v are separately generated from v cc , in a no?oad condition v + and v will be symmetrical. older charge pump approaches that generate v from v + will show a decrease in the magnitude of v compared to v + due to the inherent inefficiencies in the design. figure 20. auto on-line timing waveforms receiver rs-232 input voltages status +5v 0v -5v t stsl t stsh t online v cc 0v driver rs-232 output voltages 0v +2.7v -2.7v s h u t d o w n the clock rate for the charge pump typically operates at 250khz. the external capacitors can be as low as 0.1 f with a 16v breakdown voltage rating.
date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation 14 figure 22. charge pump ?phase 2 figure 23. charge pump waveforms v cc = +5v ?0v v ss storage capacitor v dd storage capacitor c 1 c 2 c 3 c 4 + + ++ figure 24. charge pump ?phase 3 v cc = +5v ?v +5v ?v v ss storage capacitor v dd storage capacitor c 1 c 2 c 3 c 4 + + ++ figure 25. charge pump ?phase 4 v cc = +5v +10v v ss storage capacitor v dd storage capacitor c 1 c 2 c 3 c 4 + + ++ v cc = +5v ?v ?v +5v v ss storage capacitor v dd storage capacitor c 1 c 2 c 3 c 4 + + ++ figure 21. charge pump ?phase 1 ch1 2.00v ch2 2.00v m 1.00 s ch1 1.96v 2 1 t t [] t 2 +6v a) c 2+ b) c 2 - -6v 0v 0v
15 date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation figure 26. sp3243eb driver output voltages vs. load current per transmitter figure 27. circuit for the connectivity of the sp3243eb with a db-9 connector 6 4 2 0 -2 -4 -6 tr ansmitter output voltage [v] load current per transmitter [ma] v out+ v out- 0.62 0.869 0.939 1.02 1.12 1.23 1.38 1.57 1.82 2.67 3.46 4.93 8.6 6 7 8 9 1 2 3 4 5 db-9 connector 6. dce ready 7. request to send 8. clear to send 9. ring indicator db-9 connector pins: 1. received line signal detector 2. received data 3. transmitted data 4. data terminal ready 5. signal ground (common) sp3243eb 28 24 2 1 27 3 26 5k ? 5k ? 5k ? 5k ? 5k ? gnd c1+ c1- c2+ c2- v+ v- v cc 14 13 12 20 19 18 17 16 15 0.1 f 0.1 f 0.1 f + c2 c5 c1 + + c3 c4 + + 0.1 f 0.1 f 9 10 11 4 5 6 7 8 to p supervisor circuit 23 22 21 v cc v cc 25 t 1 in r 1 out r 1 in t 2 out r 2 out t 2 in t 3 in t 3 out t 1 out r 2 in r 3 in r 4 in r 5 in r 2 out r 3 out r 4 out r 5 out online shutdown status
date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation 16 table 3. auto on-line logic figure 28. stage i of auto on-line circuitry figure 29. stage ii of auto on-line circuitry rs-232 receiver block r x inact inactive detection block r x in r x out r 1 inact r 2 inact r 3 inact r 4 inact r 5 inact delay stage delay stage delay stage delay stage delay stage shutdown status rs - 232 signal shutdown online input status output tranceiver at receiver input status input yes high low high normal operation (auto on-line ) no high high low normal operation no high low low sutdown (auto on-line ) yes low high/low high shutdown no low high/low low shutdown
17 date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation auto on-line circuitry the sp3223eb and sp3243eb devices have a patent pending auto on-line circuitry on board that saves power in applications such as laptop computers, palmtop (pda) computers, and other portable systems. the sp3223eb and sp3243eb devices incorpo- rate an auto on-line circuit that automati- cally enables itself when the external transmit- ters are enabled and the cable is connected. conversely, the auto on-line circuit also disables most of the internal circuitry when the device is not being used and goes into a standby mode where the device typically draws 1 a. this function can also be externally controlled by the online pin. when this pin is tied to a logic low, the auto on-line function is active. once active, the device is enabled until there is no activity on the receiver inputs. the receiver input typically sees at least 3v, which are generated from the transmitters at the other end of the cable with a 5v minimum. when the external transmitters are disabled or the cable is disconnected, the receiver inputs will be pulled down by their internal 5k ? resistors to ground. when this occurs over a period of time, the internal transmitters will be disabled and the device goes into a shutdown or standby mode. when online is high, the auto on-line mode is disabled. the auto on-line circuit has two stages: 1) inactive detection 2) accumulated delay the first stage, shown in figure 28 , detects an inactive input. a logic high is asserted on r x inact if the cable is disconnected or the external transmitters are disabled. otherwise, r x inact will be at a logic low. this circuit is duplicated for each of the other receivers. the second stage of the auto on-line cir- cuitry, shown in figure 29 , processes all the receiver's r x inact signals with an accumu- lated delay that disables the device to a 1 a supply current. the status pin goes to a logic low when the cable is disconnected, the external transmitters are disabled, or the shutdown pin is invoked. the typical accumulated delay is around 20 s. when the sp3223eb and sp3243eb drivers or internal charge pump are disabled, the supply current is reduced to 1 a. this can commonly occur in hand-held or portable applications where the rs-232 cable is disconnected or the rs-232 drivers of the connected peripheral are turned off. the auto on-line mode can be disabled by the shutdown pin. if this pin is a logic low, the auto on-line function will not operate regardless of the logic state of the online pin. table 3 summarizes the logic of the auto on- line operating modes. the truth table logic of the sp3223eb and sp3243eb driver and re- ceiver outputs can be found in table 2. the status pin outputs a logic low signal if the device is shutdown. this pin goes to a logic high when the external transmitters are enabled and the cable is connected. when the sp3223eb and sp3243eb devices are shut down, the charge pumps are turned off. v+ charge pump output decays to v cc , the v- output decays to gnd. the decay time will depend on the size of capacitors used for the charge pump. once in shutdown, the time required to exit the shut down state and have valid v+ and v- levels is typically 200 s. for easy programming, the status can be used to indicate dtr or a ring indicator signal. tying online and shutdown together will bypass the auto on-line circuitry so this connection acts like a shutdown input pin.
date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation 18 esd tolerance the sp3223eb/3243eb series incorporates ruggedized esd cells on all driver output and receiver input pins. the esd structure is improved over our previous family for more rugged applications and environments sensitive to electro-static discharges and associated transients. the improved esd tolerance is at least +15kv without damage nor latch-up. there are different methods of esd testing applied: a) mil-std-883, method 3015.7 b) iec1000-4-2 air-discharge c) iec1000-4-2 direct contact the human body model has been the generally accepted esd testing method for semiconductors. this method is also specified in mil-std-883, method 3015.7 for esd testing. the premise of this esd test is to simulate the human body? potential to store electrostatic energy and discharge it to an integrated circuit. the simulation is performed by using a test model as shown in figure 30 . this method will test the ic? capability to withstand an esd transient during normal handling such as in manufacturing areas where the ics tend to be handled frequently. the iec-1000-4-2, formerly iec801-2, is generally used for testing esd on equipment and systems. for system manufacturers, they must guarantee a certain amount of esd protection since the system itself is exposed to the outside environment and human presence. the premise with iec1000-4-2 is that the system is required to withstand an amount of static electricity when esd is applied to points and surfaces of the equipment that are accessible to personnel during normal usage. the transceiver ic receives most of the esd current when the esd source is applied to the connector pins. the test circuit for iec1000-4-2 is shown on figure 31 . there are two methods within iec1000-4-2, the air discharge method and the contact discharge method. with the air discharge method, an esd voltage is applied to the equipment under test (eut) through air. this simulates an electrically charged person ready to connect a cable onto the rear of the system only to find an unpleasant zap just before the person touches the back panel. the high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she even touches the system. this energy, whether discharged directly or through air, is predominantly a function of the discharge current rather than the discharge voltage. variables with an air discharge such as approach speed of the object carrying the esd potential to the system and humidity will tend to change the discharge current. for example, the rise time of the discharge current varies with the approach speed. the contact discharge method applies the esd current directly to the eut. this method was devised to reduce the unpredictability of the esd arc. the discharge current rise time is constant since the energy is directly transferred without the air-gap arc. in situations such as hand held systems, the esd charge can be directly discharged to the equipment from a person already holding the equipment. the current is transferred on to the keypad or the serial port of the equipment directly and then travels through the pcb and finally to the ic. r c c s r s sw1 sw2 r c device under t est dc power source c s r s sw1 sw2 figure 30. esd test circuit for human body model
19 date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation device pin human body iec1000-4-2 tested model air discharge direct contact level driver outputs 15kv 15kv 8kv 4 receiver inputs 15kv 15kv 8kv 4 r s and r v add up to 330 ? f or iec1000-4-2. r s and r v add up to 330 ? for iec1000-4-2. contact-discharge module r v r c c s r s sw1 sw2 r c device under t est dc power source c s r s sw1 sw2 r v contact-discharge module the circuit model in figures 29 and 30 represent the typical esd testing circuit used for all three methods. the c s is initially charged with the dc power supply when the first switch (sw1) is on. now that the capacitor is charged, the second switch (sw2) is on while sw1 switches off. the voltage stored in the capacitor is then applied through r s , the current limiting resistor, onto the device under test (dut). in esd tests, the sw2 switch is pulsed so that the device under test receives a duration of voltage. for the human body model, the current limiting resistor (r s ) and the source capacitor (c s ) are 1.5k ? an 100pf, respectively. for iec-1000-4- 2, the current limiting resistor (r s ) and the source capacitor (c s ) are 330 ? an 150pf, respectively. the higher c s value and lower r s value in the iec1000-4-2 model are more stringent than the human body model. the larger storage capacitor injects a higher voltage to the test point when sw2 is switched on. the lower current limiting resistor increases the current charge onto the test point. figure 32. esd test waveform for iec1000-4-2 t=0ns t=30ns 0a 15a 30a t ? i ? figure 31. esd test circuit for iec1000-4-2 table 4. transceiver esd tolerance levels
date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation 20 d alternate end pins (both ends) d1 = 0.005" min. (0.127 min.) e p ackage: plastic dual?n?ine (narrow) a = 0.210" max. (5.334 max). e1 c l a2 a1 = 0.015" min. (0.381min.) b b1 e = 0.100 bsc (2.540 bsc) e a = 0.300 bsc (7.620 bsc) dimensions (inches) minimum/maximum (mm) a2 b b1 c d e e1 l 16?in 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.780/0.800 (19.812/20.320) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0 / 15 (0 /15 ) 20?in 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 0.980/1.060 (24.892/26.924) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0 / 15 (0 /15 ) 28?in 0.115/0.195 (2.921/4.953) 0.014/0.022 (0.356/0.559) 0.045/0.070 (1.143/1.778) 0.008/0.014 (0.203/0.356) 1.385/1.454 (35.17/36.90) 0.300/0.325 (7.620/8.255) 0.240/0.280 (6.096/7.112) 0.115/0.150 (2.921/3.810) 0 / 15 (0 /15 )
21 date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation d eh p ackage: plastic shrink small outline (ssop) dimensions (inches) minimum/maximum (mm) 20?in a a1 l b e a a1 b d e e h l 0.068/0.078 (1.73/1.99) 0.002/0.008 (0.05/0.21) 0.010/0.015 (0.25/0.38) 0.278/0.289 (7.07/7.33) 0.205/0.212 (5.20/5.38) 0.0256 bsc (0.65 bsc) 0.301/0.311 (7.65/7.90) 0.022/0.037 (0.55/0.95) 0 /8 (0 /8 ) 24?in 0.068/0.078 (1.73/1.99) 0.002/0.008 (0.05/0.21) 0.010/0.015 (0.25/0.38) 0.317/0.328 (8.07/8.33) 0.205/0.212 (5.20/5.38) 0.0256 bsc (0.65 bsc) 0.301/0.311 (7.65/7.90) 0.022/0.037 (0.55/0.95) 0 /8 (0 /8 ) 28?in 0.068/0.078 (1.73/1.99) 0.002/0.008 (0.05/0.21) 0.010/0.015 (0.25/0.38) 0.397/0.407 (10.07/10.33) 0.205/0.212 (5.20/5.38) 0.0256 bsc (0.65 bsc) 0.301/0.311 (7.65/7.90) 0.022/0.037 (0.55/0.95) 0 /8 (0 /8 ) 16?in 0.068/0.078 (1.73/1.99) 0.002/0.008 (0.05/0.21) 0.010/0.015 (0.25/0.38) 0.239/0.249 (6.07/6.33) 0.205/0.212 (5.20/5.38) 0.0256 bsc (0.65 bsc) 0.301/0.311 (7.65/7.90) 0.022/0.037 (0.55/0.95) 0 /8 (0 /8 )
date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation 22 d eh p ackage: plastic small outline (soic) (wide) a a1 l b e dimensions (inches) minimum/maximum (mm) a a1 b d e e h l 28?in 0.090/0.104 (2.29/2.649) 0.004/0.012 (0.102/0.300) 0.013/0.020 (0.330/0.508) 0.697/0.713 (17.70/18.09) 0.291/0.299 (7.402/7.600) 0.050 bsc (1.270 bsc) 0.394/0.419 (10.00/10.64) 0.016/0.050 (0.406/1.270) 0 /8 (0 /8 )
23 date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation gage plane 1.0 oia e 0.169 (4.30) 0.177 (4.50) 0.252 bsc (6.4 bsc) 0?8 12?ef 0.039 (1.0) e/2 0.039 (1.0) 0.126 bsc (3.2 bsc) d 0.007 (0.19) 0.012 (0.30) 0.033 (0.85) 0.037 (0.95) 0.002 (0.05) 0.006 (0.15) 0.043 (1.10) max ( 3) 1.0 ref 0.020 (0.50) 0.026 (0.75) ( 1) 0.004 (0.09) min 0.004 (0.09) min 0.010 (0.25) ( 2) 0.008 (0.20) dimensions in inches (mm) minimum/maximum symbol 20 lead 28 lead d 0.252/0.260 0.378/0.386 (6.40/6.60) (9.60/9.80) e 0.026 bsc 0.026 bsc (0.65 bsc) (0.65 bsc) p ackage: plastic thin small outline (tssop)
date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation 24 d2 nx k nx l e2 nx k nx b 0.80 0.90 1.00 0 0.02 0.05 dimensions in (mm) 32 pin qfn jedecmo220 (vhhd-4) 0 0.65 1.00 0.20 ref 0.35 0.40 0.45 a a1 a2 a3 d e d2 l min nom max 3.50 3.65 3.80 e2 3.50 3.65 3.80 nd 5.00 bsc 5.00 bsc 8 ne 8 32 pin qfn e 0.50 bsc b 0.18 0.25 0.30 0? - 14 n 32 e d e seating plane a1 a 4x a3 a2 k 0.20 - - package: 32 pin qfn
25 date: 6/2/04 sp3223eb/3243eb +3.0v to +5.5v rs-232 transceivers ?copyright 2004 sipex corporation part number temperature range package types sp3223ebcp .................................................... 0 c to +70 c -------------------------------------------- 20-pin pdip sp3223ebca .................................................... 0 c to +70 c ------------------------------------------- 20-pin ssop sp3223ebca/tr .............................................. 0 c to +70 c ------------------------------------------- 20-pin ssop sp3223ebcy .................................................... 0 c to +70 c ----------------------------------------- 20-pin tssop sp3223ebcy/tr .............................................. 0 c to +70 c ----------------------------------------- 20-pin tssop sp3223ebep .................................................. -40 c to +85 c ------------------------------------------- 20-pin pdip sp3223ebea .................................................. -40 c to +85 c ------------------------------------------ 20-pin ssop sp3223ebea/tr ............................................ -40 c to +85 c ------------------------------------------ 20-pin ssop sp3223ebey .................................................. -40 c to +85 c ---------------------------------------- 20-pin tssop sp3223ebey/tr ............................................ -40 c to +85 c ---------------------------------------- 20-pin tssop sp3243ebct .................................................... 0 c to +70 c ----------------------------------------- 28-pin wsoic sp3243ebct/tr .............................................. 0 c to +70 c ----------------------------------------- 28-pin wsoic sp3243ebca .................................................... 0 c to +70 c ------------------------------------------- 28-pin ssop sp3243ebca/tr .............................................. 0 c to +70 c ------------------------------------------- 28-pin ssop sp3243ebcy ................................................... -0 c to +70 c ----------------------------------------- 28-pin tssop sp3243ebcy/tr ............................................. -0 c to +70 c ----------------------------------------- 28-pin tssop sp3243ebcr ................................................... -0 c to +70 c --------------------------------------------- 32-pin qfn sp3243ebcr/tr ............................................. -0 c to +70 c --------------------------------------------- 32-pin qfn sp3243ebet .................................................. -40 c to +85 c ---------------------------------------- 28-pin wsoic sp3243ebet/tr ............................................ -40 c to +85 c ---------------------------------------- 28-pin wsoic sp3243ebea .................................................. -40 c to +85 c ------------------------------------------ 28-pin ssop sp3243ebea/tr ............................................ -40 c to +85 c ------------------------------------------ 28-pin ssop sp3243ebey .................................................. -40 c to +85 c ---------------------------------------- 28-pin tssop sp3243ebey/tr ............................................ -40 c to +85 c ---------------------------------------- 28-pin tssop sp3243eber .................................................. -40 c to +85 c -------------------------------------------- 32-pin qfn sp3243eber/tr ............................................ -40 c to +85 c -------------------------------------------- 32-pin qfn corporation analog excellence sipex corporation reserves the right to make changes to any products described herein. sipex does not assume any liability aris ing out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor t he rights of others. sipex corporation headquarters and sales office 233 south hillview drive milpitas, ca 95035 tel: (408) 934-7500 fax: (408) 935-7600 available in lead free packaging. to order add "-l" suffix to part number. example: sp3243ebcy /tr = standard; sp3243ebcy -l/tr = lead free /tr = tape and reel pack quantity is 1,500 for ssop, tssop and wsoic. pack quantity is 2,500 qfn ordering information date revision description 6/2/04 a added qfn package. revision history

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